Recently, attention has been focused on an information processing apparatus that causes a programmable device, which is a field-programmable gate array (FPGA) or the like and dynamically reconfigures logic, to function as an accelerator. In an information processing apparatus of this type, in the case where multiple circuits are sequentially programmed in an FPGA and multiple processes are executed, a portion common to the multiple circuits and a portion not overlapping individual portions of the multiple circuits are programmed in the FPGA in advance. After that, a time period for reconfiguring logic is reduced by programming a portion overlapping the individual portions of the circuits in the FPGA at the time of the execution of the processes of the multiple circuits (see, for example, Japanese Laid-open Patent Publication No, 2001-51826).
When a load of a process executed by a circuit programmed in the FPGA increases, the efficiency of the process is improved by copying, to the FPGA, the circuit that executes the process and causing the multiple circuits to execute the process in parallel (see, for example, Japanese Laid-open Patent Publication No. 2000-148707). When the FPGA has multiple divided regions that are program units of the circuits, whether an available divided region is suitable for the shape of a circuit to be programmed in the FPGA is determined based on information of the shape of the circuit. When the available divided region is suitable for the information of the shape of the circuit, the circuit is programmed in the suitable available divided region (see, for example, Japanese Laid-open Patent Publication No. 2015-39155).